? semiconductor components industries, llc, 2016 january, 2016 ? rev. 2 1 publication order number: cat24c32bac4/d cat24c32bc4, cat24c32bac4 32 kb i 2 c cmos serial eeprom 4-ball wlcsp description the cat24c32bc4 and cat24c32bac4 are 32?kb cmos serial eeprom devices available in a 4?ball wlcsp package. both devices are internally organized as 4096 words of 8 bits each. they feature a 32?byte page write buffer and support the standard (100 khz), fast (400 khz) and fast?plus (1 mhz) i 2 c protocol. the cat24c32bc4 and cat24c32bac4 respond to a different slave address and are therefore suitable in applications that require two serial eeprom devices with 4?ball wlcsp on the same i 2 c bus. features ? supports standard, fast and fast?plus i 2 c protocol ? 1.7 v to 5.5 v supply voltage range ? 32?byte page write buffer ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? 4?ball wlcsp package ? this device is pb?free, halogen free/bfr free, and rohs compliant figure 1. functional symbol sda scl cat24c32bc4 v cc v ss cat24c32bac4 www. onsemi.com pin configuration (top view) see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information serial data sda serial clock scl power supply v cc ground v ss function pin name pin function for the location of pin 1, please consult the corresponding package drawing. wlcsp?4 c4c suffix case 567jy wlcsp (c4c) a1 a2 b1 b2 sda v ss scl v cc 1 x = specific device code = b: cat24c32bc4 = j: cat24c32bac4 y = production year (last digit) m = production month (1?9, o, n, d) x ym marking diagram
cat24c32bc4, cat24c32bac4 www. onsemi.com 2 table 1. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the dc input voltage on any pin should not be lower than ?0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ?1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program/erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec?q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c. table 3. d.c. operating characteristics ( v cc = 1.7 v to 5.5 v, t a = ?40 c to +85 c, unless otherwise speci?ed.) symbol parameter test conditions min max units i ccr read current read, f scl = 1 mhz 0.4 ma i ccw write current write 0.6 ma i sb standby current all i/o pins at gnd or v cc 1 a i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage v cc 2.2 v ?0.5 v cc x 0.3 v v cc < 2.2 v ?0.5 v cc x 0.25 v v ih input high voltage v cc 2.2 v v cc x 0.7 v cc + 0.5 v v cc < 2.2 v v cc x 0.75 v cc + 0.5 v v ol output low voltage v cc 2.2 v, i ol = 3.0 ma 0.4 v v cc < 2.2 v, i ol = 1.0 ma 0.2 v table 4. pin impedance characteristics (v cc = 1.7 v to 5.5 v, t a = ?40 c to +85 c, unless otherwise speci?ed.) symbol parameter conditions max units c in (note 4) sda i/o pin capacitance v in = 0 v 8 pf c in (note 4) input capacitance (other pins) v in = 0 v 6 pf 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec?q100 and jedec test methods.
cat24c32bc4, cat24c32bac4 www. onsemi.com 3 table 5. a.c. characteristics (v cc = 1.7 v to 5.5 v, t a = ?40 c to +85 c) (note 5) symbol parameter standard fast fast?plus units min max min max min max f scl clock frequency 100 400 1,000 khz t hd:sta start condition hold time 4 0.6 0.25 s t low low period of scl clock 4.7 1.3 0.45 s t high high period of scl clock 4 0.6 0.35 s t su:sta start condition setup time 4.7 0.6 0.25 s t hd:dat data in hold time 0 0 0 s t su:dat data in setup time 250 100 50 ns t r (note 6) sda and scl rise time 1,000 300 100 ns t f (note 6) sda and scl fall time 300 300 100 ns t su:sto stop condition setup time 4 0.6 0.25 s t buf bus free time between stop and start 4.7 1.3 0.5 s t aa scl low to data out valid 3.5 0.9 0.40 s t dh (note 6) data out hold time 100 100 50 ns t i (note 6) noise pulse filtered at scl and sda inputs 50 50 50 ns t wr write cycle time 4 4 4 ms t pu (notes 6, 7) power?up to ready mode 0.35 0.35 0.35 ms product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. test conditions according to ?a.c. test conditions? table. 6. tested initially and after a design or process change that affects this parameter. 7. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels v cc 2.2 v: 0.2 x v cc to 0.8 x v cc v cc < 2.2 v: 0.15 x v cc to 0.85 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.3 x v cc , 0.7 x v cc output load current source: i ol = 3 ma (v cc 2.2 v); i ol = 1 ma (v cc < 2.2 v); c l = 100 pf
cat24c32bc4, cat24c32bac4 www. onsemi.com 4 power?on reset (por) each cat24c32bc4/cat24c32bac4 incorporates power?on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops b elow the por trigger level. this bi?directional por behavior protects the device against ?brown?out? failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. functional description the cat24c32bc4/cat24c32bac4 supports the inter?integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traffic, and slave devices which execute requests. the cat24c32bc4/cat24c32bac4 operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2?wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull?up resistors. the master provides the clock to the scl line, and either the master or the slaves drive the sda line. a ?0? is transmitted by pulling a line low and a ?1? by letting it stay high. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 2). the start consists of a high to low sda transition, while scl is high. absent the start, a slave will not respond to the master. the stop completes all commands, and consists of a low to high sda transition, while scl is high. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8?bit slave address (figure 3). the first 4 bits of the slave address are set to 1010. the next 3 bits are set to 0 0 0 ( ca t24c32bc4) or to 1 0 0 (cat24c32bac4). the last bit, r/w, specifies whether a read (1) or w rite (0) operation is to be performed. acknowledge during the 9 th clock cycle following every byte sent to the bus, the transmitter releases the sda line, allowing the receiver to respond. the receiver then either acknowledges (ack) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 4). bus timing is illustrated in figure 5. start condition stop condition sda scl figure 2. start/stop timing figure 3. slave address bits 1010 0 0 0 r/w 1010 1 0 0 r/w cat24c32bc4 cat24c32bac4
cat24c32bc4, cat24c32bac4 www. onsemi.com 5 figure 4. acknowledge timing 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack setup ( t su:dat ) ack delay ( t aa ) figure 5. bus timing scl sda in sda out t su:sta t hd:sta t hd:dat t f t low t aa t high t low t r t dh t buf t su:dat t su:sto write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?0?. the master then sends two address bytes and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 6). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri?stated and the slave does not acknowledge the master (figure 7). page write the byte w rite operation can be expanded to page w rite, by sending more than one data byte to the slave before issuing the stop condition (figure 8) . up to 32 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling as soon (and as long) as internal write is in progress, the slave will not acknowledge the master. this feature enables the master to immediately follow?up with a new read or write request, rather than wait for the maximum specified write time (t wr ) to elapse. upon receiving a noack response from the slave, the master simply repeats the request until the slave responds with ack. delivery state the cat24c32bc4/cat2 4c32bac4 is shipped erased, i.e., all bytes are ffh.
cat24c32bc4, cat24c32bac4 www. onsemi.com 6 slave address s a * * * c k a c k a c k s t o p p s t a r t a c k bus activity: master slave address byte address byte data byte figure 6. byte write sequence *a 15 ? a 12 are don?t care bits. a 15 ? a 8 a 7 ? a 0 d 7 ? d 0 * figure 7. write cycle timing stop condition start condition address ack 8th bit byte n scl sda t wr slave address s a c k a c k a c k s t a r t a c k s t o p a c k a c k p a c k bus activity: master slave address byte address byte data byte n data byte n+1 data byte n+p figure 8. page write sequence
cat24c32bc4, cat24c32bac4 www. onsemi.com 7 read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 9). the slave then returns to standby mode. selective read to read data residing at a speci?c address, the selected address must ?rst be loaded into the internal address register. this is done by starting a byte write sequence, whereby the master creates a start condition, then broadcasts a slave address with the r/w bit set to ?0? and then sends two address bytes to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 10). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmitting until the master responds with noack followed by st op (figure 11). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. figure 9. immediate read sequence and timing scl sda 8th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave figure 10. selective read sequence slave address s a c k a c k a c k s t a r t slave s a c k s t a r t p s t o p address byte address byte address n o a c k data byte bus activity: master slave figure 11. sequential read sequence s t o p p slave address a c k a c k a c k n o a c k a c k data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave
cat24c32bc4, cat24c32bac4 www. onsemi.com 8 package dimensions case 567jy issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 0.76 bsc e b 0.15 0.16 e 0.40 bsc 0.35 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 4x b 12 b a 0.05 c a a1 a2 c 0.0415 0.0715 0.76 bsc 0.05 c 2x top view side view bottom view note 3 e a2 0.255 ref pitch 0.16 4x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 recommended a1 package outline pitch die coat detail a (optional) a2 a3 a3 0.025 ref detail a ordering information device order number specific device marking package type temperature range lead finish shipping cat24c32bc4ctr b wlcsp?4 with die coat i = industrial (?40 c to +85 c) snag tape & reel, 5,000 units / reel CAT24C32BAC4CTR (note 10) j wlcsp?4 with die coat i = industrial (?40 c to +85 c) snag tape & reel, 5,000 units / reel 8. all packages are rohs?compliant (lead?free, halogen?free). 9. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. 10. this wlcsp?4 option responds to a dif ferent slave address compared to cat24c32bc4ctr. 11. caution: the eeprom devices delivered in wlcsp must never be exposed to ultra violet light. when exposed to ultra violet light the eeprom cells lose their stored data. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 cat24c32bac4/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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